POSTERS

Memory Power Consumption on Heterogeneous Memory Systems

Conference: JLESC 15th

Year: 2023

Description:

We focuses on understanding and giving a perspective on how to analyse memory energy consumption metric over dierent HMS setups. We consider, identifying and exposing the memory system in the simplest manner developers could access. E.g., a memory system with DRAM and NVM can be exposed as dierent NUMAs in some systems and their access implies binding the applications process to the kind of memory required. Then, we have selected a some memory-intensive applications that should be proled. Proling depends on the expertise of developers and also tools can give more or less information depending on their capabilities. In our case, Intel Performance Counter Monitor (PCM) enables the possibility to get some performance counters related to memory power consumption in between others related to bandwidth...






Power Consumption Metric on Heterogeneous Memory Systems

Conference: The 5th R-CCS International Symposium

Year: 2023

Description:

We have focused on the metric related to the power consumption of the memory system. We present a methodology that allows developers to have a deeper knowledge about the power consumption of each type of memory involved, as well as give an ordering that can be used for cases where power must be saved, or when it is needed to have a balance between power consumption and the performance of an application. We also present in this work an early prediction model that allows obtaining the possible behaviour of an application before a given memory system without actually having it at hand.






M&MMs: Navigating Complex Memory Spaces with hwloc

Conference: MEMSYS '19

Year: 2019

Description:

In this work, we present M&MMs, an interface to help manage the memory system complexity. It is comprised of a set of memory attributes and an API to express and manage the diverse memory characteristics using high-level metrics that are easy to understand. Our goal is to establish a building block to enable next-generation runtime systems, computing libraries, and scientific applications to leverage the best performance attributes of each memory, e.g., leverage the bandwidth of the fastest memory with the capacity of the largest memory...

Link: https://doi.org/10.1145/3357526.3357546

https://hal.archives-ouvertes.fr/hal-02266285/