Publications
Conference: Parallel Computing Journal
Year: 2023
Description:
High-performance computing developers must prepare their runtimes and applications for these architectures, even before they are actually available. Hence, we survey software solutions for emulating them. First, we list many ways to modify the performance of platforms so that developers may test their code under different memory performance profiles. This is required to identify kernels and data buffers that are sensitive to memory performance.
Then, we present several techniques for exposing fake heterogeneous memory information to the software stack. This is useful for adapting runtimes and applications to heterogeneous memory so that different kinds of memory are detected at runtime and so that buffers are allocated in the appropriate one...
Using Performance Attributes for Managing Heterogeneous Memory in HPC Applications
Conference: PDSEC - IPDPS22
Year: 2022
Description:
The complexity of memory systems has increased considerably over the past decade. Supercomputers may now include several levels of heterogeneous and non-uniform memory, with significantly different properties in terms of performance, capacity, persistence, etc. Developers of scientific applications face a huge challenge: efficiently exploit the memory system to improve performance, but keep productivity high by using portable solutions. In this work, we present a new API and a method to manage the complexity of modern memory systems...
Exposer les caractéristiques des architectures à mémoires hétérogènes aux applications parallèles
Conference: COMPAS 2020
Year: 2020
Description:
La complexité des systèmes de mémoire a considérablement augmenté au cours de la dernière décennie. En conséquence, les supercalculateurs incluent des mémoires à plusieurs niveaux, hétérogènes et non uniformes, avec propriétés significativement différentes...
M&MMs: Navigating Complex Memory Spaces with hwloc
Conference: MEMSYS '19
Year: 2019
Description:
In this work, we present M&MMs, an interface to help manage the memory system complexity. It is comprised of a set of memory attributes and an API to express and manage the diverse memory characteristics using high-level metrics that are easy to understand. Our goal is to establish a building block to enable next-generation runtime systems, computing libraries, and scientific applications to leverage the best performance attributes of each memory, e.g., leverage the bandwidth of the fastest memory with the capacity of the largest memory...
Opportunities for Partitioning Non-Volatile Memory DIMMs between Co-scheduled Jobs on HPC Nodes
Conference: Euro-Par 2019
Year: 2019
Description:
The emergence of non-volatile memory DIMMs such as Intel Optane DCPMM blurs the gap between usual volatile memory and persistent storage by enabling byte-accessible persistent memory with reasonable performance. This new hardware supports many possible use cases for high-performance applications, from high performance storage to very-high-capacity volatile memory (terabytes)...